OPENCORES.ORG
.
 
-- VHDL structural description generated from `ram`

-- date : Tue Feb 20 23:00:09 2001

 

-- Entity Declaration

ENTITY ram IS

PORT (

rws : in BIT; -- rws

cs : in BIT; -- cs

res : in BIT; -- res

c : in BIT_VECTOR (0 TO 15); -- c

io0 : inout BIT; -- io0

io1 : inout BIT; -- io1

io2 : inout BIT; -- io2

io3 : inout BIT; -- io3

io4 : inout BIT; -- io4

io5 : inout BIT; -- io5

io6 : inout BIT; -- io6

io7 : inout BIT; -- io7

vdd : in BIT; -- vdd

vss : in BIT -- vss

);

END ram;

-- Architecture Declaration

ARCHITECTURE VST OF ram IS

COMPONENT a2_y

port (

i0 : in BIT; -- i0

i1 : in BIT; -- i1

t : out BIT; -- t

vdd : in BIT; -- vdd

vss : in BIT -- vss

);

END COMPONENT;

COMPONENT mc

port (

x : in BIT; -- x

res : in BIT; -- res

rowsel : in BIT; -- rowsel

wren : in BIT; -- wren

y : out BIT; -- y

vdd : in BIT; -- vdd

vss : in BIT -- vss

);

END COMPONENT;

COMPONENT p1_y

port (

i : in BIT; -- i

t : out BIT; -- t

vdd : in BIT; -- vdd

vss : in BIT -- vss

);

END COMPONENT;

SIGNAL in0 : BIT; -- in0

SIGNAL in1 : BIT; -- in1

SIGNAL in2 : BIT; -- in2

SIGNAL in3 : BIT; -- in3

SIGNAL in4 : BIT; -- in4

SIGNAL in5 : BIT; -- in5

SIGNAL in6 : BIT; -- in6

SIGNAL in7 : BIT; -- in7

SIGNAL q0 : BIT; -- q0

SIGNAL q1 : BIT; -- q1

SIGNAL q2 : BIT; -- q2

SIGNAL q3 : BIT; -- q3

SIGNAL q4 : BIT; -- q4

SIGNAL q5 : BIT; -- q5

SIGNAL q6 : BIT; -- q6

SIGNAL q7 : BIT; -- q7

SIGNAL wren : BIT; -- wren

BEGIN

and1 : a2_y

PORT MAP (

vss => vss,

vdd => vdd,

t => wren,

i1 => cs,

i0 => rws);

bufi7 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in7,

i => io7);

bufi6 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in6,

i => io6);

bufi5 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in5,

i => io5);

bufi4 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in4,

i => io4);

bufi3 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in3,

i => io3);

bufi2 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in2,

i => io2);

bufi1 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in1,

i => io1);

bufi0 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => in0,

i => io0);

mc07 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(0));

mc06 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(0));

mc05 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(0));

mc04 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(0));

mc03 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(0));

mc02 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(0));

mc01 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(0));

mc00 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(0));

mc17 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(1));

mc16 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(1));

mc15 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(1));

mc14 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(1));

mc13 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(1));

mc12 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(1));

mc11 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(1));

mc10 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(1));

mc27 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(2));

mc26 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(2));

mc25 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(2));

mc24 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(2));

mc23 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(2));

mc22 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(2));

mc21 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(2));

mc20 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(2));

mc37 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(3));

mc36 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(3));

mc35 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(3));

mc34 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(3));

mc33 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(3));

mc32 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(3));

mc31 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(3));

mc30 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(3));

mc47 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(4));

mc46 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(4));

mc45 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(4));

mc44 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(4));

mc43 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(4));

mc42 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(4));

mc41 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(4));

mc40 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(4));

mc57 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(5));

mc56 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(5));

mc55 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(5));

mc54 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(5));

mc53 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(5));

mc52 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(5));

mc51 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(5));

mc50 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(5));

mc67 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(6));

mc66 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(6));

mc65 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(6));

mc64 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(6));

mc63 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(6));

mc62 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(6));

mc61 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(6));

mc60 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(6));

mc77 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(7));

mc76 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(7));

mc75 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(7));

mc74 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(7));

mc73 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(7));

mc72 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(7));

mc71 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(7));

mc70 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(7));

mc87 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(8));

mc86 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(8));

mc85 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(8));

mc84 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(8));

mc83 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(8));

mc82 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(8));

mc81 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(8));

mc80 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(8));

mc97 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(9));

mc96 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(9));

mc95 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(9));

mc94 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(9));

mc93 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(9));

mc92 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(9));

mc91 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(9));

mc90 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(9));

mc107 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(10));

mc106 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(10));

mc105 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(10));

mc104 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(10));

mc103 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(10));

mc102 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(10));

mc101 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(10));

mc100 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(10));

mc117 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(11));

mc116 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(11));

mc115 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(11));

mc114 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(11));

mc113 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(11));

mc112 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(11));

mc111 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(11));

mc110 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(11));

mc127 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(12));

mc126 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(12));

mc125 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(12));

mc124 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(12));

mc123 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(12));

mc122 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(12));

mc121 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(12));

mc120 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(12));

mc137 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(13));

mc136 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(13));

mc135 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(13));

mc134 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(13));

mc133 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(13));

mc132 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(13));

mc131 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(13));

mc130 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(13));

mc147 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(14));

mc146 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(14));

mc145 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(14));

mc144 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(14));

mc143 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(14));

mc142 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(14));

mc141 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(14));

mc140 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(14));

mc157 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q7,

wren => res,

rowsel => in7,

res => wren,

x => c(15));

mc156 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q6,

wren => res,

rowsel => in6,

res => wren,

x => c(15));

mc155 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q5,

wren => res,

rowsel => in5,

res => wren,

x => c(15));

mc154 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q4,

wren => res,

rowsel => in4,

res => wren,

x => c(15));

mc153 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q3,

wren => res,

rowsel => in3,

res => wren,

x => c(15));

mc152 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q2,

wren => res,

rowsel => in2,

res => wren,

x => c(15));

mc151 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q1,

wren => res,

rowsel => in1,

res => wren,

x => c(15));

mc150 : mc

PORT MAP (

vss => vss,

vdd => vdd,

y => q0,

wren => res,

rowsel => in0,

res => wren,

x => c(15));

bufo7 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io7,

i => q7);

bufo6 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io6,

i => q6);

bufo5 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io5,

i => q5);

bufo4 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io4,

i => q4);

bufo3 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io3,

i => q3);

bufo2 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io2,

i => q2);

bufo1 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io1,

i => q1);

bufo0 : p1_y

PORT MAP (

vss => vss,

vdd => vdd,

t => io0,

i => q0);

end VST;

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Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.