(See change Log at bottom of page for changes/updates)
 

Description

This is a advanced Memory Controller intended for embedded applications. Some of the features are:

• SDRAM, SSRAM, FLASH, ROM and many other devices supported
• 8 Chip selects, each uniquely programmable
• Flexible timing to accommodate a variety of memory devices
• Burst transfers and burst termination
• Performance optimization by leaving active rows open
• Default boot sequence support
• Dynamic bus sizing for reading from Async. Devices
• Byte parity Generation and Checking
• Multi Master memory bus support
• Industry standard WISHBONE SoC host interface
• Up to 8 * 128 Mbyte memory size
• Supports Power Down Mode

Status

• 8/2/2001 I have fixed various bugs and made many small changes and am still trying to improve and debug the memory controller further.
• New Directory Structure ! We have agreed on a common directory structure at OpenCores.
• PLEASE HELP: I'm looking for people to help me verify the core
• I will post a message to cores@opencores.org_NOSPAM each time I have an update

Downloading

To get a tared and gziped snapshot from CVS click here, or go to the CVS info page.

The latest Specification is available here: mc_doc.pdf (about 260K)

Author / Maintainer

I have been doing ASIC design, verification and synthesis for over 15 years. I hope you find this cores useful. Please send me a note if you intend to use it  !

Rudolf Usselmann
rudi@asics.ws_NOSPAM
www.asics.ws

Feel free to send me comments, suggestions and bug reports.

Change Log

8/2/2001 Many Bug Fixes and Changes, Directory Structure Update
13/5/2001 Core Done Update
19/4/2001 Updates List of Features
7/4/2001 RU Initial web page