Core Description:
Robotic arm controller core where Stepper motor have been
used as an arm driver is developed in VHDL.
Functionality:
To control the stepping speed of stepper motor
by full step mode
half step mode.
To control the stepping direction of stepper motor
by clockwise mode
anticlockwise mode.
Interfacing Card:
Here collector of 4 darlington pair transistors are
connected to the windings of Stepper motor & a
free-wheeling diode is connected across each winding for
fast switching.
NOTE:
Time delay between each Stepping sequence should be 1 to
5msec.
For implementing this Core in FPGA use appropriate clock
divider.
Component description
| Component name | Description |
|---|---|
| COUNTER_F | Counter for the generation of full step control signals. |
| FULL STEP | Module gives clockwise & anticlockwise control signals for full step mode. |
| STEPPER_F | Module gives control signal to stepper motor for full step mode It is a structural module contains counter_f,full_step as components. |
| COUNTER_H | Counter for generation of half step control signals. |
| HALF_STEP | Module gives clockwise & anticlockwise control signals for halfstep mode. |
| STEPPER_H | Module gives control signal to stepper motor for half step mode. It is a structural module contains counter_h,half_step as components |
| SEL_MUX | Module selects full step or half step mode depending upon STEP_SEL control signal. |
| ROBO_ARM | TOP LEVEL DESIGN OF ROBOTIC ARM CONTROLLER Control of two Step modes(full,half) & two Direction(clockwise & anticlockwise) It is a strutural description contains stepper_f ,stepper_h,sel_mux as components. |
| Signal name | Description |
|---|---|
| CLK | Robotic arm clock signal |
| STOP | Robotic arm Stop signal |
| DIR_SEL | Robotic arm Direction select signal (Clockwise or Anticlockwise) |
| STEP_SEL | Robotic arm Step action select select signal (full\half) |
| ARM_IN | Robotic arm output control signal. |
| DATA_OUT | Robotic arm output control signal. for full step |
| DATA_OUT_H | Robotic arm output control signal. for Half step |
| ARM | Output control signal from sel_mux. |
| DOUT_H | Output counter signal from counter_h. |
| DOUT | Output counter signal from counter_f. |
Author: R.Sathishkumar sathishr@opencores.org
VHDL CODE :
------------------------------------------------------------------------------
-- Title : COUNTER_F
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : COUNTER_F.vhd
-- Author : R.SATHISH KUMAR
-- Created : 25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
-- This vhdl module is a counter.
-- for generation of full step control signals.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.std_arith.all;
entity counter_f is
port(CLK : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DOUT : buffer STD_LOGIC_VECTOR(1 downto 0));
end counter_f;
architecture behave of counter_f is
signal count : std_logic_vector(1 downto 0);
begin
process(CLK ,STOP,STEP_SEL )
begin
if(CLK 'event and CLK ='1')then
if(STOP ='1')then
count<=count;
elsif(STEP_SEL = '1') then
count<=count+1;
end if;
end if;
DOUT <=count;
end process;
end behave;
------------------------------------------------------------------------------
-- Title : FULL STEP
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : full_step.vhd
-- Author : R.SATHISH KUMAR
-- Created : 25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
-- This vhdl module gives clockwise & anticlockwise control
signals for -- fullstep mode.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity full_step is
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0));
end full_step;
architecture behave of full_step is
begin
process(CLK,DIN,DIR_SEL)
begin
if (CLK'event and CLK ='1')then
if(DIR_SEL ='1')then
if(DIN="00")then
Y<="0011";
elsif(DIN="01")then
Y<="0110";
elsif(DIN="10")then
Y<="1100";
elsif(DIN="11")then
Y<="1001";
end if;
elsif(DIR_SEL ='0')then
if(DIN="00")then
Y<="1100";
elsif(DIN="01")then
Y<="0110";
elsif(DIN="10")then
Y<="0011";
elsif(DIN="11")then
Y<="1001";
end if;
end if;
end if;
end process;
end behave;
------------------------------------------------------------------------------
-- Title : STEPPER_F
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : stepper_f.vhd
-- Author : R.SATHISH KUMAR
-- Created :25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
-- This vhdl module gives control signal to stepper motor for
full step -- mode
-- It is a structural module contains counter_f,full_step as
components
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.std_arith.all;
entity stepper_f is
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(3 downto 0));
end stepper_f;
architecture toplevel of stepper_f is
component counter_f
port(CLK : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DOUT : buffer STD_LOGIC_VECTOR(1 downto 0));
end component;
component full_step
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0));
end component;
signal dout:std_logic_vector(1 downto 0);
signal y : std_logic_vector(3 downto 0);
begin
u1 : counter_f port map (CLK,STEP_SEL,STOP ,DOUT);
u2 : full_step port map (CLK,DIR_SEL,DOUT,Y);
DATA_OUT<=Y;
end toplevel;
------------------------------------------------------------------------------
-- Title : COUNTER_H
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : counter_h.vhd
-- Author : R.SATHISH KUMAR
-- Created : 25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
-- This vhdl module is a counter.
-- for generation of half step control signals.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.std_arith.all;
entity counter_h is
port(CLK : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DOUT_H : buffer STD_LOGIC_VECTOR(2 downto 0));
end counter_h;
architecture behave of counter_h is
signal count_h : std_logic_vector(2 downto 0);
begin
process(CLK ,STOP,STEP_SEL)
begin
if(CLK 'event and CLK ='1')then
if(STOP ='1')then
count_h<=count_h;
elsif(STEP_SEL = '0') then
count_h<=count_h+1;
end if;
end if;
DOUT_H<=count_h;
end process;
end behave;
------------------------------------------------------------------------------
-- Title : HALF_STEP
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : half_step.vhd
-- Author : R.SATHISH KUMAR
-- Created : 25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
-- This vhdl module gives clockwise & anticlockwise control
signals for --halfstep mode.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.std_arith.all;
entity half_step is
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
DIN_H: in STD_LOGIC_VECTOR(2 downto 0);
Y_H : out STD_LOGIC_VECTOR(3 downto 0));
end half_step;
architecture behave of half_step is
begin
process(CLK ,DIN_H,DIR_SEL)
begin
if (CLK 'event and CLK ='1')then
if(DIR_SEL ='1')then --counter clockwise pattern
if(DIN_H="000")then
Y_H<="0011";
elsif(DIN_H="001")then
Y_H<="0010";
elsif(DIN_H="010")then
Y_H<="0110";
elsif(DIN_H="011")then
Y_H<="0100";
elsif(DIN_H="100")then
Y_H<="1100";
elsif(DIN_H="101")then
Y_H<="1000";
elsif(DIN_H="110")then
Y_H<="1001";
elsif(DIN_H="111")then
Y_H<="0001";
end if;
elsif(DIR_SEL ='0')then --clockwise pattern
if(DIN_H="000")then
Y_H<="1100";
elsif(DIN_H="001")then
Y_H<="0100";
elsif(DIN_H="010")then
Y_H<="0110";
elsif(DIN_H="011")then
Y_H<="0010";
elsif(DIN_H="100")then
Y_H<="0011";
elsif(DIN_H="101")then
Y_H<="0001";
elsif(DIN_H="110")then
Y_H<="1001";
elsif(DIN_H="111")then
Y_H<="1000";
end if;
end if;
end if;
end process;
end behave;
------------------------------------------------------------------------------
-- Title : STEPPER_H
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : stepper_h.vhd
-- Author : R.SATHISH KUMAR
-- Created : 25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
-- This vhdl module gives control signal to stepper motor for
half step --mode
-- It is a structural module contains counter_h,half_step as
components
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.std_arith.all;
entity stepper_h is
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DATA_OUT_H : out std_logic_vector(3 downto 0));
end stepper_h;
architecture toplevel_h of stepper_h is
component counter_h
port(CLK : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DOUT_H : buffer STD_LOGIC_VECTOR(2 downto 0));
end component;
component half_step
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
DIN_H: in STD_LOGIC_VECTOR(2 downto 0);
Y_H : out STD_LOGIC_VECTOR(3 downto 0));
end component;
signal dout_h:std_logic_vector(2 downto 0);
signal y_h : std_logic_vector(3 downto 0);
begin
u_h1 : counter_h port map (CLK,STEP_SEL,STOP,DOUT_H);
u_h2 : half_step port map (CLK,DIR_SEL,DOUT_H,Y_H);
DATA_OUT_H <= Y_H;
end toplevel_h;
------------------------------------------------------------------------------
-- Title : SEL_MUX
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : sel_mux.vhd
-- Author : R.SATHISH KUMAR
-- Created : 25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
-- This vhdl module selects full step or half step mode depending
upon
--STEP_SEL control signal.
----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.std_arith.all;
entity sel_mux is
port( DATA_OUT : in STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT_H : in STD_LOGIC_VECTOR(3 downto 0);
STEP_SEL: in STD_LOGIC;
ARM:out STD_LOGIC_VECTOR(3 downto 0));
end sel_mux;
architecture bhv of sel_mux is
begin
ARM <= DATA_OUT when STEP_SEL = '1' else
DATA_OUT_H ;
end bhv;
------------------------------------------------------------------------------
-- Title : ROBO_ARM
-- Project : ROBOTIC ARM CONTROLLER
-------------------------------------------------------------------------------
-- File : robo_arm.vhd
-- Author : R.SATHISH KUMAR
-- Created : 25-4-2001
-- Last update :
-------------------------------------------------------------------------------
-- Description:
--This vhdl module is a TOP LEVEL DESIGN OF ROBOTIC ARM
CONTROLLER
--Possible control of two step modes(full,half) & two
direction(clockwise & anticlockwise)
--It is a strutural description contains stepper_f
,stepper_h,sel_mux as components
-----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.std_arith.all;
entity robo_arm is
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC; --direction select
STOP :in STD_LOGIC; --stop
STEP_SEL:in STD_LOGIC; --step action select(full\half)
ARM_IN:out STD_LOGIC_VECTOR(3 downto 0));
end robo_arm;
architecture TOP of robo_arm is
component stepper_f
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(3 downto 0));
end component;
component stepper_h
port(CLK : in STD_LOGIC;
DIR_SEL : in STD_LOGIC;
STEP_SEL:in STD_LOGIC;
STOP :in STD_LOGIC;
DATA_OUT_H : out std_logic_vector(3 downto 0));
end component;
component sel_mux
port( DATA_OUT : in STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT_H : in STD_LOGIC_VECTOR(3 downto 0);
STEP_SEL: in STD_LOGIC;
ARM:out STD_LOGIC_VECTOR(3 downto 0));
end component;
signal data_out: std_logic_vector(3 downto 0);
signal data_out_h : std_logic_vector(3 downto 0);
signal arm : std_logic_vector(3 downto 0);
begin
T1: stepper_f port map (CLK ,DIR_SEL,STEP_SEL,STOP,DATA_OUT);
T2: stepper_h port map (CLK ,DIR_SEL,STEP_SEL,STOP,DATA_OUT_H);
T3: sel_mux port map ( DATA_OUT,DATA_OUT_H,STEP_SEL,ARM);
ARM_IN <= ARM;
end TOP;