WisboneTK

WishboneTK bus resizer

Description

WishboneTK bus resizer converts an X-bit Wishbone bus access to an Y-bit bus access. The conversion is done by asserting the correct byte select signals and multiplex the data-bus according to the access. The core cannot change the granularity of the access. It is 100% Wishbone compatible with the WishboneTK extensions. The device contains only simple logic with no feed-back thus it is asyncronous without any state. For this reason the CLK_I and RST_I signals, required for most Wishbone devies are not used. The core can do up- and down-size. If master and slave interface has the same size, the core compiles into a bunch of wires except for Wishbone extension gates.

Wishbone datasheet

DescriptionSpecification
General Description Bus up-sizer.
Supported cycles Slave read/write
Slave block read/write
Slave rmw
Master read/write
Master block read/write
Master rmw
Data port size Configurable on both slave and master side
Data port granularity 8-bit
Data port maximum operand size Bus size
Data transfer ordering Little and big endien
Data transfer sequencing n/a
Supported signal list and cross reference to equivalent Wishbone signals
Signal nameWishbone equiv.
Signals to connect to master
M_CYC_I CYC_I
M_STB_I STB_I
M_WE_I WE_I
M_ACK_O ACK_O
M_RTY_O RTY_O
M_ERR_O ERR_O
M_SEL_I(..) SEL_I()
M_ADR_I(..) ADR_I()
M_DAT_I(..) DAT_I()
M_DAT_O(..) DAT_O()
Signals to connect to slave
S_CYC_O CYC_O
S_STB_O STB_O
S_WE_O WE_O
S_ACK_I ACK_I
S_RTY_I RTY_I
S_ERR_I ERR_I
S_SEL_O(..) SEL_O()
S_ADR_O(..) ADR_O()
S_DAT_I(..) DAT_I()
S_DAT_O(..) DAT_O()

Parameter description

Parameter nameDescription
m_bus_width Master data bus width.
m_addr_width Master address bus width
s_bus_width Slave data bus width.
little_endien True for little endien, False for big endien address decoding

Signal description

Signal nameDescription
Signals to connect to master
M_CYC_I Wishbone cycle signal. High value frames blocks of access
M_STB_I Wishbone strobe signal. High value indicates cycle to this particular device
M_WE_I Wishbone write enable signal. High indicates data flowing from master to slave
M_ACK_O Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
M_ACK_OI WhisboneTK acknowledge chain input signal
M_RTY_O Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block.
M_RTY_OI WhisboneTK retry chain input signal
M_ERR_O Wishbone error signal. High indicates that slave cannot complete the last cycle in the block.
M_ERR_OI WhisboneTK error chain input signal
M_ADR_I(m_addr_width-1..0) Wishbone address bus signals
M_SEL_I(m_bus_width/8-1..0) Wishbone byte-selection signals
M_DAT_I(m_bus_width-1..0) Wishbone data bus input (to slave direction) signals
M_DAT_O(m_bus_width-1..0) Wishbone data bus output (to master direction) signals
M_DAT_OI(m_bus_width-1..0) WhisboneTK data bus chain input signal
Signals to connect to slave
S_CYC_O Wishbone cycle signal. High value frames blocks of access
S_STB_O Wishbone strobe signal. High value indicates cycle to this particular device
S_WE_O Wishbone write enable signal. High indicates data flowing from master to slave
S_ACK_I Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
S_RTY_I Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block.
S_ERR_I Wishbone error signal. High indicates that slave cannot complete the last cycle in the block.
S_ADR_O(m_addr_width-2..0) Wishbone address bus signals
S_SEL_O(s_bus_width/8-1..0) Wishbone byte-selection signals
S_DAT_I(s_bus_width-1..0) Wishbone data bus input (to slave direction) signals
S_DAT_O(s_bus_width-1..0) Wishbone data bus output (to master direction) signals

Author & Maintainer

Andras Tantos