head 1.2; access; symbols r0_0_1:1.1.1.1 uiuc:1.1.1; locks; strict; comment @# @; 1.2 date 2005.10.10.22.52.13; author zuofu; state Exp; branches; next 1.1; commitid 572434af0884567; 1.1 date 2005.09.11.10.29.48; author zuofu; state Exp; branches 1.1.1.1; next ; commitid 469e4324071a4567; 1.1.1.1 date 2005.09.11.10.29.48; author zuofu; state Exp; branches; next ; commitid 469e4324071a4567; desc @@ 1.2 log @GPU HDL design mostly done, intro is now completely working with XSA-50/100 + PIC microcontroller. Working on schematic and ARM processor support. @ text @--ECE395 GPU: --Top Level HDL --===================================================== --Designed by: --Zuofu Cheng --James Cavanaugh --Eric Sands -- --of the University of Illinois at Urbana Champaign --under the direction of Dr. Lippold Haken --==================================================== --Based in part on Doug Hodson's work which in turn --was based off of the XSOC from Gray Research LLC. -- --release under the GNU General Public License --and kindly hosted by www.opencores.org @ 1.1 log @Initial revision @ text @@ 1.1.1.1 log @First Checkin! Using the XESS dual ported RAM controller and the original XSOC (retromicro) VGA driver. Also included a whole bunch of misc stuff.... @ text @@