head 1.2; access; symbols ver_tag:1.1.1.1 vendor_tag:1.1.1; locks; strict; comment @# @; 1.2 date 2008.08.10.17.21.32; author dimo; state Exp; branches; next 1.1; commitid 7413489f23774567; 1.1 date 2008.06.23.19.57.52; author dimo; state Exp; branches 1.1.1.1; next ; commitid 1b3f4860003f4567; 1.1.1.1 date 2008.06.23.19.57.52; author dimo; state Exp; branches; next ; commitid 1b3f4860003f4567; desc @@ 1.2 log @ALu bug removed. Improved testbench @ text @[Library] others = $MODEL_TECH/../modelsim.ini simprim = $XILINX/modelsim-6.3d/simprim unisim = $XILINX/modelsim-6.3d/unisim xilinxcorelib = $XILINX/modelsim-6.3d/XilinxCoreLib work = modelsim/work [vcom] ; Turn on VHDL-1993 as the default. Normally is off (VHDL-1987). ; VHDL93 = 1 ; Show source line containing error. Default is off. ; Show_source = 1 ; Turn off unbound-component warnings. Default is on. ; Show_Warning1 = 0 ; Turn off process-without-a-wait-statement warnings. Default is on. ; Show_Warning2 = 0 ; Turn off null-range warnings. Default is on. ; Show_Warning3 = 0 ; Turn off no-space-in-time-literal warnings. Default is on. ; Show_Warning4 = 0 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. ; Show_Warning5 = 0 ; Turn off optimization for IEEE std_logic_1164 package. Default is on. ; Optimize_1164 = 0 ; Turn on resolving of ambiguous function overloading in favor of the ; "explicit" function declaration (not the one automatically created by ; the compiler for each type declaration). Default is off. ; .ini file has Explict enable so that std_logic_signed/unsigned ; will match synthesis tools behavior. Explicit = 1 ; Turn off VITAL compliance checking. Default is checking on. ; NoVitalCheck = 1 ; Ignore VITAL compliance checking errors. Default is to not ignore. ; IgnoreVitalErrors = 1 ; Turn off VITAL compliance checking warnings. Default is to show warnings. ; Show_VitalChecksWarnings = false ; Change case statement static errors to warnings. Default is to give an error. ; NoCaseStaticError = 1 ; Disable errors caused by aggregates that are not locally static. ; Default is to give an error. ; NoOthersStaticError = 1 ; Turn off acceleration of the VITAL packages. Default is to accelerate. ; NoVital = 1 ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on some limited synthesis rule compliance checking. Checks only: ; -- signals used (read) by a process must be in the sensitivity list ; CheckSynthesis = 1 ; Activate optimizations on expressions that don't involve signals, ; waits, or function/procedure/task invocations. Default is off. ; ScalarOpts = 1 ; Require the user to specify a configuration for all bindings, ; and do not generate a compile time default binding for the ; component. This will result in an elaboration error of ; 'component not bound' if the user fails to do so. Avoids the rare ; issue of a false dependency upon the unused default binding. ; RequireConfigForAllDefaultBinding = 1 VHDL93 = 2002 NoDebug = 0 CheckSynthesis = 0 NoVitalCheck = 0 Optimize_1164 = 1 NoVital = 0 Quiet = 0 Show_source = 0 DisableOpt = 0 VcomZeroIn = 0 CoverageNoSub = 0 NoCoverage = 0 Coverage = sbceft CoverCells = 1 CoverExcludeDefault = 0 CoverOpt = 2 Show_Warning1 = 1 Show_Warning2 = 1 Show_Warning3 = 1 Show_Warning4 = 1 Show_Warning5 = 1 [vlog] ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on Verilog hazard checking (order-dependent accessing of global vars). ; Default is off. ; Hazard = 1 ; Turn on converting regular Verilog identifiers to uppercase. Allows case ; insensitivity for module names. Default is no conversion. ; UpCase = 1 ; Turns on incremental compilation of modules ; Incremental = 1 vlog95compat = 0 Vlog01Compat = 0 Svlog = 0 Coverage = sbceft CoverCells = 1 CoverExcludeDefault = 0 CoverOpt = 2 OptionFile = /export/jack/dimo/vhdl/cpu_2/vlog.opt Quiet = 0 Show_source = 0 Protect = 0 NoDebug = 0 Hazard = 0 UpCase = 0 DisableOpt = 0 VlogZeroIn = 0 [vsim] ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = ps ; User time unit for run commands ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the ; unit specified for Resolution. For example, if Resolution is 100ps, ; then UserTimeUnit defaults to ps. UserTimeUnit = default ; Default run length RunLength = 100 ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 ; Directive to license manager: ; vhdl Immediately reserve a VHDL license ; vlog Immediately reserve a Verilog license ; plus Immediately reserve a VHDL and Verilog license ; nomgc Do not look for Mentor Graphics Licenses ; nomti Do not look for Model Technology Licenses ; noqueue Do not wait in the license queue when a license isn't available ; License = plus ; Stop the simulator after an assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal BreakOnAssertion = 3 ; Assertion Message Format ; %S - Severity Level ; %R - Report Message ; %T - Time of assertion ; %D - Delta ; %I - Instance or Region pathname (if available) ; %% - print '%' character ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" ; Assertion File - alternate file for storing assertion messages ; AssertFile = assert.log ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned DefaultRadix = symbolic ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history ;CommandHistory = cmdhist.log ; Specify whether paths in simulator commands should be described ; in VHDL or Verilog format. For VHDL, PathSeparator = / ; for Verilog, PathSeparator = . PathSeparator = / ; Specify the dataset separator for fully rooted contexts. ; The default is ':'. For example, sim:/top ; Must not be the same character as PathSeparator. DatasetSeparator = : ; Disable assertion messages ; IgnoreNote = 1 ; IgnoreWarning = 1 ; IgnoreError = 1 ; IgnoreFailure = 1 ; Default force kind. May be freeze, drive, or deposit ; or in other terms, fixed, wired or charged. ; DefaultForceKind = freeze ; If zero, open files when elaborated ; else open files on first read or write ; DelayFileOpen = 0 ; Control VHDL files opened for write ; 0 = Buffered, 1 = Unbuffered UnbufferedOutput = 0 ; Control number of VHDL files open concurrently ; This number should always be less then the ; current ulimit setting for max file descriptors ; 0 = unlimited ConcurrentFileLimit = 40 ; This controls the number of hierarchical regions displayed as ; part of a signal name shown in the waveform window. The default ; value or a value of zero tells VSIM to display the full name. ; WaveSignalNameWidth = 0 ; Turn off warnings from the std_logic_arith, std_logic_unsigned ; and std_logic_signed packages. ; StdArithNoWarnings = 1 ; Turn off warnings from the IEEE numeric_std and numeric_bit ; packages. ; NumericStdNoWarnings = 1 ; Control the format of a generate statement label. Don't quote it. ; GenerateFormat = %s__%d ; Specify whether checkpoint files should be compressed. ; The default is to be compressed. ; CheckpointCompressMode = 0 ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriuser.sl ; Specify default options for the restart command. Options can be one ; or more of: -force -nobreakpoint -nolist -nolog -nowave ; DefaultRestartOptions = -force ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs ; (> 500 megabyte memory footprint). Default is disabled. ; Specify number of megabytes to lock. ; LockedMemory = 1000 VoptFlow = 1 [lmc] ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software libsm = $MODEL_TECH/libsm.sl ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) ; libsm = $MODEL_TECH/libsm.dll ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so ; Logic Modeling's SmartModel SWIFT software (Windows NT) ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll ; ModelSim's interface to Logic Modeling's hardware modeler SFI software libhm = $MODEL_TECH/libhm.sl ; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) ; libhm = $MODEL_TECH/libhm.dll ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) ; libsfi = /lib/hp700/libsfi.sl ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) ; libsfi = /lib/rs6000/libsfi.a ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) ; libsfi = /lib/sun4.solaris/libsfi.so ; Logic Modeling's hardware modeler SFI software (Windows NT) ; libsfi = /lib/pcnt/lm_sfi.dll [sccom] UseScv = 0 UseScMs = 0 CppOptions = SccomVerbose = 0 @ 1.1 log @Initial revision @ text @d81 21 d122 16 d141 1 a141 1 Resolution = ns d259 1 d286 5 @ 1.1.1.1 log @first upload @ text @@