head 1.5; access; symbols rel_1_1:1.5 rel_1_0:1.4 rel_0_6_1_beta:1.3 rel_0_6__beta:1.3 rel_0_6_beta:1.3 rel_0_5_beta:1.1 rel_0_1_beta:1.1 rel_0_2_beta:1.1 rel_0_3_beta:1.1 rel_0_4_beta:1.1; locks; strict; comment @# @; 1.5 date 2008.04.29.21.16.26; author arniml; state Exp; branches; next 1.4; commitid 54c481790294567; 1.4 date 2006.07.21.23.29.13; author arniml; state Exp; branches; next 1.3; commitid 32bd44c1633a4567; 1.3 date 2005.10.15.21.10.55; author arniml; state Exp; branches; next 1.2; commitid 79d44351705c4567; 1.2 date 2004.12.02.07.14.33; author arniml; state Exp; branches; next 1.1; 1.1 date 2004.09.16.20.45.00; author arniml; state Exp; branches; next ; desc @@ 1.5 log @update to new mnemonic decoder @ text @ Compile list for the T48 uController project ============================================ Version: $Date: 2006/07/21 23:29:13 $ $Name: $ bench/vhdl/if_timing.vhd bench/vhdl/if_timing-c.vhd rtl/vhdl/t48_pack-p.vhd rtl/vhdl/psw.vhd rtl/vhdl/psw-c.vhd rtl/vhdl/pmem_ctrl_pack-p.vhd rtl/vhdl/pmem_ctrl.vhd rtl/vhdl/pmem_ctrl-c.vhd rtl/vhdl/p2.vhd rtl/vhdl/p2-c.vhd rtl/vhdl/p1.vhd rtl/vhdl/p1-c.vhd rtl/vhdl/timer.vhd rtl/vhdl/timer-c.vhd rtl/vhdl/dmem_ctrl_pack-p.vhd rtl/vhdl/dmem_ctrl.vhd rtl/vhdl/dmem_ctrl-c.vhd rtl/vhdl/decoder_pack-p.vhd rtl/vhdl/cond_branch_pack-p.vhd rtl/vhdl/alu_pack-p.vhd rtl/vhdl/t48_comp_pack-p.vhd rtl/vhdl/int.vhd rtl/vhdl/int-c.vhd rtl/vhdl/t48_tb_pack-p.vhd rtl/vhdl/decoder.vhd rtl/vhdl/decoder-c.vhd rtl/vhdl/db_bus.vhd rtl/vhdl/db_bus-c.vhd rtl/vhdl/cond_branch.vhd rtl/vhdl/cond_branch-c.vhd rtl/vhdl/clock_ctrl.vhd rtl/vhdl/clock_ctrl-c.vhd rtl/vhdl/bus_mux.vhd rtl/vhdl/bus_mux-c.vhd rtl/vhdl/alu.vhd rtl/vhdl/alu-c.vhd rtl/vhdl/t48_core.vhd rtl/vhdl/t48_core-c.vhd rtl/vhdl/system/generic_ram_ena.vhd rtl/vhdl/system/generic_ram_ena-c.vhd rtl/vhdl/system/lpm_rom.vhd rtl/vhdl/t48_core_comp_pack-p.vhd bench/vhdl/tb.vhd bench/vhdl/tb-c.vhd Elaborate tb_behav_c0 rtl/vhdl/system/t48_rom-e.vhd bench/vhdl/t48_rom-lpm-a.vhd bench/vhdl/t48_rom-lpm-c.vhd rtl/vhdl/system/t8048_notri.vhd rtl/vhdl/system/t8048_notri-c.vhd rtl/vhdl/system/t48_system_comp_pack-p.vhd rtl/vhdl/system/t8048.vhd rtl/vhdl/system/t8048-c.vhd bench/vhdl/tb_t8048.vhd bench/vhdl/tb_t8048-c.vhd Elaborate tb_t8048_behav_c0 rtl/vhdl/system/t8039_notri.vhd rtl/vhdl/system/t8039_notri-c.vhd rtl/vhdl/system/t8039.vhd rtl/vhdl/system/t8039-c.vhd bench/vhdl/tb_t8039.vhd bench/vhdl/tb_t8039-c.vhd Elaborate tb_t8039_behav_c0 rtl/vhdl/t8243/t8243_core.vhd rtl/vhdl/t8243/t8243_core-c.vhd rtl/vhdl/t8243/t8243_comp_pack-p.vhd rtl/vhdl/t8243/t8243_async_notri.vhd rtl/vhdl/t8243/t8243_async_notri-c.vhd rtl/vhdl/t8243/t8243.vhd rtl/vhdl/t8243/t8243-c.vhd bench/vhdl/tb_t8048_t8243.vhd bench/vhdl/tb_t8048_t8243-c.vhd Elaborate tb_t8048_t8243_behav_c0 rtl/vhdl/t8243/t8243_sync_notri.vhd rtl/vhdl/t8243/t8243_sync_notri-c.vhd bench/vhdl/tb_t8243.vhd bench/vhdl/tb_t8243-c.vhd Elaborate tb_t8243_behav_c0 @ 1.4 log @update list for inclusion of t8243 testbenches @ text @d4 2 a5 2 Version: $Date: 2005/10/15 21:10:55 $ $Name$ a24 2 rtl/vhdl/opc_table.vhd rtl/vhdl/opc_table-c.vhd a27 2 rtl/vhdl/opc_decoder.vhd rtl/vhdl/opc_decoder-c.vhd @ 1.3 log @update list for Wishbone toplevel @ text @d4 2 a5 1 Version: $Date: 2004/12/02 07:14:33 $ d49 2 a50 4 rtl/vhdl/system/lpm_ram_dq.vhd rtl/vhdl/system/syn_ram-e.vhd rtl/vhdl/system/syn_ram-lpm-a.vhd rtl/vhdl/system/syn_ram-lpm-c.vhd d55 5 a59 3 rtl/vhdl/system/syn_rom-e.vhd rtl/vhdl/system/syn_rom-lpm-a.vhd rtl/vhdl/system/syn_rom-lpm-c.vhd d67 2 d75 18 a92 4 rtl/vhdl/system/wb_master.vhd rtl/vhdl/system/wb_master-c.vhd rtl/vhdl/system/t8050_wb.vhd rtl/vhdl/system/t8050_wb-c.vhd @ 1.2 log @added hierarchy t8048_notri and system components package @ text @d4 1 a4 1 Version: $Date: 2004/09/16 20:45:00 $ d66 2 d72 4 @ 1.1 log @initial check-in @ text @d4 1 a4 1 Version: $Date$ d59 3 @