head 1.1; access; symbols; locks; strict; comment @# @; 1.1 date 2006.06.13.00.53.35; author joff; state Exp; branches; next ; commitid 21b4448e0ae24567; desc @@ 1.1 log @Initial import of ts7300_opencore. Quartus II project tree for Technologic Systems TS-7300 FPGA Linux Computer. Contains WISHBONE bridge verilog as well as pin locks, timing constraints, and various other Quartus II project metadata. Also included is a sample implementation of the open-ethernet core as well as a stub WISHBONE slave demonstrating a 32-bit register in the address space of the ARM9 CPU running Linux. @ text @[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 [ProjectWorkspace.Frames.ChildFrames.Document-2] ptn_Child1=ViewFrame-0 [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] DocPathName=ts7300_top.v DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPOGAAAAAABJAAAAAAODEAAAAAPPBAAAAA IsActiveChildFrame=True ptn_Child1=StateMap [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap] AFC_IN_REPORT=False @