head 1.4; access; symbols a01:1.1.1.1 tantos:1.1.1; locks; strict; comment @# @; 1.4 date 2003.11.20.05.07.57; author tantos; state Exp; branches; next 1.3; 1.3 date 2001.04.27.14.26.59; author tantos; state Exp; branches; next 1.2; 1.2 date 2001.04.25.15.05.30; author tantos; state Exp; branches; next 1.1; 1.1 date 2001.04.11.12.18.00; author tantos; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2001.04.11.12.18.00; author tantos; state Exp; branches; next ; desc @@ 1.4 log @Large update to new version of wb_tk. Major changes: - Xilinx support added - Altera support is poor: though it's there I haven't tested or even compiled it for quite some time - Behavioral models are added - Async master is completely new: it's much more complicated but actually works - Cores are tested in real HW (x2s300e) - wb_out_reg currently lacks byte-select support - wb_in_reg is added as a trivial input register @ text @-- -- Technology mapping library. Interface. -- -- (c) Copyright Andras Tantos 2001/03/31 -- This code is distributed under the terms and conditions of the GNU General Public Lince. -- library IEEE; use IEEE.std_logic_1164.all; package technology is -- originaly in synopsys. Naming convention is changed to resolve potential name conflict. function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR; function to_integer(arg:std_logic_vector) return integer; -- function add_one(inp : std_logic_vector) return std_logic_vector; -- function sub_one(inp : std_logic_vector) return std_logic_vector; function is_zero(inp : std_logic_vector) return boolean; function sl(l: std_logic_vector; r: integer) return std_logic_vector; function sr(l: std_logic_vector; r: integer) return std_logic_vector; -- function "+"(op_l, op_r: std_logic_vector) return std_logic_vector; -- function "-"(op_l, op_r: std_logic_vector) return std_logic_vector; function log2(inp : integer) return integer; function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer; function size2bits(inp : integer) return integer; function max2(a : integer; b: integer) return integer; function min2(a : integer; b: integer) return integer; function equ(a : std_logic_vector; b : integer) return boolean; component d_ff port ( d : in STD_LOGIC; clk: in STD_LOGIC; ena: in STD_LOGIC := '1'; clr: in STD_LOGIC := '0'; pre: in STD_LOGIC := '0'; q : out STD_LOGIC ); end component; component spmem generic ( default_out : std_logic := 'X'; -- Default output default_content : std_logic := '0'; -- Simple initialization data adr_width : integer := 3; dat_width : integer := 8; async_read : boolean := true ); port ( stb_i : std_logic; -- chip select clk_i : in std_logic; -- write clock adr_i : in std_logic_vector(adr_width -1 downto 0); -- Address dat_i : in std_logic_vector(dat_width -1 downto 0); -- input data dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output Data we_i : in std_logic; -- Read Write Enable ack_o : out std_logic -- Ready output ); end component; component dpmem generic ( default_out : std_logic := 'X'; -- Default output default_content : std_logic := '0'; -- Simple initialization data adr_width : integer := 3; dat_width : integer := 8; async_read : boolean := true ); port ( -- Signals for the port A a_clk_i : in std_logic; -- Read clock a_stb_i : in std_logic; -- Read port select a_we_i : in std_logic; -- Read port Write enable a_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Read Address a_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data a_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data a_ack_o : out std_logic; -- Read ready output -- Signals for the port B b_clk_i : in std_logic; -- Write clock b_stb_i : in std_logic; -- Write port select b_we_i : in std_logic; -- Write Enable b_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Write Address b_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data b_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data b_ack_o : out std_logic -- Write ready output ); end component; component fifo generic ( default_out : std_logic := 'X'; -- Default output default_content : std_logic := '0'; -- Simple initialization data adr_width : integer := 3; dat_width : integer := 8; async_read : boolean := true -- Controls memory only. For FIFO logic clock is still needed. ); port ( reset : in std_logic; -- System reset r_clk_i : in std_logic; -- Read clock r_stb_i : in std_logic; -- Read port select r_we_i : in std_logic := '0'; -- Read port Write enable (should be '0') r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out r_ack_o : out std_logic; -- Read ready output w_clk_i : in std_logic; -- Write clock w_stb_i : in std_logic; -- Write port select w_we_i : in std_logic := '1'; -- Write port write enable w_dat_i : in std_logic_vector(dat_width-1 downto 0); -- Data in w_ack_o : out std_logic; -- Write ready output full_o : out std_logic; -- Full Flag (combinational) empty_o : out std_logic; -- Empty flag (combinational) used_o : out std_logic_vector(adr_width downto 0) -- number of data in the fifo (combinational) ); end component; end technology; library IEEE; use IEEE.std_logic_1164.all; entity spmem is generic ( default_out : std_logic := 'X'; -- Default output default_content : std_logic := '0'; -- Simple initialization data adr_width : integer := 3; dat_width : integer := 8; async_read : boolean := true ); port ( stb_i : std_logic; -- chip select clk_i : in std_logic; -- write clock adr_i : in std_logic_vector(adr_width -1 downto 0); -- Address dat_i : in std_logic_vector(dat_width -1 downto 0); -- input data dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output Data we_i : in std_logic; -- Read Write Enable ack_o : out std_logic -- Ready output ); end spmem; library IEEE; use IEEE.std_logic_1164.all; entity dpmem is generic ( default_out : std_logic := 'X'; -- Default output default_content : std_logic := '0'; -- Simple initialization data adr_width : integer := 3; dat_width : integer := 8; async_read : boolean := true ); port ( -- Signals for the port A a_clk_i : in std_logic; -- Read clock a_stb_i : in std_logic; -- Read port select a_we_i : in std_logic; -- Read port Write enable a_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Read Address a_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data a_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data a_ack_o : out std_logic; -- Read ready output -- Signals for the port B b_clk_i : in std_logic; -- Write clock b_stb_i : in std_logic; -- Write port select b_we_i : in std_logic; -- Write Enable b_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Write Address b_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data b_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data b_ack_o : out std_logic -- Write ready output ); end dpmem; library IEEE; use IEEE.std_logic_1164.all; entity fifo is generic ( default_out : std_logic := 'X'; -- Default output default_content : std_logic := '0'; -- Simple initialization data adr_width : integer := 3; dat_width : integer := 8; async_read : boolean := true -- Controls memory only. For FIFO logic clock is still needed. ); port ( reset : in std_logic; -- System reset r_clk_i : in std_logic; -- Read clock r_stb_i : in std_logic; -- Read port select r_we_i : in std_logic := '0'; -- Read port Write enable (should be '0') r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out r_ack_o : out std_logic; -- Read ready output w_clk_i : in std_logic; -- Write clock w_stb_i : in std_logic; -- Write port select w_we_i : in std_logic := '1'; -- Write port write enable w_dat_i : in std_logic_vector(dat_width-1 downto 0); -- Data in w_ack_o : out std_logic; -- Write ready output full_o : out std_logic; -- Full Flag (combinational) empty_o : out std_logic; -- Empty flag (combinational) used_o : out std_logic_vector(adr_width downto 0) -- number of data in the fifo (combinational) ); end fifo; library IEEE; use IEEE.std_logic_1164.all; entity d_ff is port ( d : in STD_LOGIC; clk: in STD_LOGIC; ena: in STD_LOGIC := '1'; clr: in STD_LOGIC := '0'; pre: in STD_LOGIC := '0'; q : out STD_LOGIC ); end d_ff; @ 1.3 log @Minor changes @ text @d2 1 a2 1 -- Technology mapping library. ALTERA edition. a9 2 library exemplar; use exemplar.exemplar_1164.all; d12 6 a17 1 function add_one(inp : std_logic_vector) return std_logic_vector; d19 4 a22 3 function sl(l: std_logic_vector; r: integer) return std_logic_vector; -- procedure inc(data : inout std_logic_vector); function "+"(op_l, op_r: std_logic_vector) return std_logic_vector; d26 1 a26 1 function max(a : integer; b: integer) return integer; d30 8 a37 7 component d_ff is port ( d : in STD_LOGIC; clk: in STD_LOGIC; ena: in STD_LOGIC := '1'; clr: in STD_LOGIC := '0'; pre: in STD_LOGIC := '0'; q : out STD_LOGIC d40 53 a92 4 component fifo is generic (fifo_width : positive; used_width : positive; fifo_depth : positive d94 18 a111 10 port (d_in : in std_logic_vector(fifo_width-1 downto 0); clk : in std_logic; wr : in std_logic; rd : in std_logic; a_clr : in std_logic := '0'; s_clr : in std_logic := '0'; d_out : out std_logic_vector(fifo_width-1 downto 0); used : out std_logic_vector(used_width-1 downto 0); full : out std_logic; empty : out std_logic a114 107 library IEEE; use IEEE.std_logic_1164.all; library exemplar; use exemplar.exemplar_1164.all; library synopsys; use synopsys.std_logic_arith.all; package body technology is function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is begin return exemplar_1164."+"(op_l, op_r); end; function add_one(inp : std_logic_vector) return std_logic_vector is variable one: std_logic_vector(inp'RANGE) := (others => '0'); begin one(0) := '1'; return exemplar_1164."+"(inp,one); end; function is_zero(inp : std_logic_vector) return boolean is variable zero: std_logic_vector(inp'RANGE) := (others => '0'); begin return (inp = zero); end; function sl(l: std_logic_vector; r: integer) return std_logic_vector is begin return exemplar_1164.sl(l,r); end; -- procedure inc(data : inout std_logic_vector) is -- begin -- data := addone(data); -- end; function max(a : integer; b: integer) return integer is begin if (a > b) then return a; end if; return b; end; function min2(a : integer; b: integer) return integer is begin if (a < b) then return a; end if; return b; end; function log2(inp : integer) return integer is begin if (inp < 1) then return 0; end if; if (inp < 2) then return 0; end if; if (inp < 4) then return 1; end if; if (inp < 8) then return 2; end if; if (inp < 16) then return 3; end if; if (inp < 32) then return 4; end if; if (inp < 64) then return 5; end if; if (inp < 128) then return 6; end if; if (inp < 256) then return 7; end if; if (inp < 512) then return 8; end if; if (inp < 1024) then return 9; end if; if (inp < 2048) then return 10; end if; if (inp < 4096) then return 11; end if; if (inp < 8192) then return 12; end if; if (inp < 16384) then return 13; end if; if (inp < 32768) then return 14; end if; if (inp < 65538) then return 15; end if; return 16; end; function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is begin if (in_bus = out_bus) then return 0; end if; if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if; if (in_bus > out_bus) then return log2(in_bus/out_bus); end if; end; function size2bits(inp : integer) return integer is begin if (inp < 1) then return 1; end if; if (inp < 2) then return 1; end if; if (inp < 4) then return 2; end if; if (inp < 8) then return 3; end if; if (inp < 16) then return 4; end if; if (inp < 32) then return 5; end if; if (inp < 64) then return 6; end if; if (inp < 128) then return 7; end if; if (inp < 256) then return 8; end if; if (inp < 512) then return 9; end if; if (inp < 1024) then return 10; end if; if (inp < 2048) then return 11; end if; if (inp < 4096) then return 12; end if; if (inp < 8192) then return 13; end if; if (inp < 16384) then return 14; end if; if (inp < 32768) then return 15; end if; if (inp < 65538) then return 16; end if; return 17; end; function equ(a : std_logic_vector; b : integer) return boolean is variable b_s : std_logic_vector(a'RANGE); begin b_s := CONV_STD_LOGIC_VECTOR(b,a'HIGH+1); return (a = b_s); end; end package body technology; d119 7 a125 10 library exemplar; use exemplar.exemplar_1164.all; library lpm; use lpm.all; entity fifo is generic (fifo_width : positive; used_width : positive; fifo_depth : positive d127 10 a136 55 port (d_in : in std_logic_vector(fifo_width-1 downto 0); clk : in std_logic; wr : in std_logic; rd : in std_logic; a_clr : in std_logic := '0'; s_clr : in std_logic := '0'; d_out : out std_logic_vector(fifo_width-1 downto 0); used : out std_logic_vector(used_width-1 downto 0); full : out std_logic; empty : out std_logic ); end fifo; architecture altera of fifo is component lpm_fifo generic (LPM_WIDTH : positive; LPM_WIDTHU : positive; LPM_NUMWORDS : positive; LPM_SHOWAHEAD : string := "OFF"; LPM_TYPE : string := "LPM_FIFO"; LPM_HINT : string := "UNUSED"); port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); CLOCK : in std_logic; WRREQ : in std_logic; RDREQ : in std_logic; ACLR : in std_logic; SCLR : in std_logic; Q : out std_logic_vector(LPM_WIDTH-1 downto 0); USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0); FULL : out std_logic; EMPTY : out std_logic); end component; begin altera_fifo: lpm_fifo generic map ( LPM_WIDTH => fifo_width, LPM_WIDTHU => used_width, LPM_NUMWORDS => fifo_depth, LPM_SHOWAHEAD => "OFF", LPM_TYPE => "LPM_FIFO", LPM_HINT => "UNUSED" ) port map ( DATA => d_in, CLOCK => clk, WRREQ => wr, RDREQ => rd, ACLR => a_clr, SCLR => s_clr, Q => d_out, USEDW => used, FULL => full, EMPTY => empty ); end altera; d141 28 a168 75 library exemplar; use exemplar.exemplar_1164.all; library lpm; use lpm.all; entity ram is generic ( data_width : positive; addr_width : positive ); port ( clk : in std_logic; we : in std_logic; addr : in std_logic_vector(addr_width-1 downto 0); d_in : in std_logic_vector(data_width-1 downto 0); d_out : out std_logic_vector(data_width-1 downto 0) ); end ram; architecture altera of ram is component lpm_ram_dp generic ( lpm_width: positive; lpm_widthad: positive; lpm_numwords: natural := 0; lpm_type: string := "lpm_ram_dp"; lpm_indata: string := "REGISTERED"; lpm_outdata: string := "UNREGISTERED"; lpm_rdaddress_control: string := "REGISTERED"; lpm_wraddress_control: string := "REGISTERED"; lpm_file: string := "UNUSED"; lpm_hint: string := "UNUSED" ); port ( rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0); rdclock, wrclock: in std_logic := '0'; rden, rdclken, wrclken: in std_logic := '1'; wren: in std_logic; data: in std_logic_vector(lpm_width-1 downto 0); q: out std_logic_vector(lpm_width-1 downto 0) ); end component; begin altera_ram: lpm_ram_dp generic map ( lpm_width => data_width, lpm_widthad => addr_width, lpm_numwords => 2 ** addr_width, lpm_type => "lpm_ram_dp", lpm_indata => "REGISTERED", lpm_wraddress_control => "REGISTERED", lpm_outdata => "UNREGISTERED", lpm_rdaddress_control => "UNREGISTERED", lpm_file => "UNUSED", lpm_hint => "UNUSED" ) port map ( -- rdclock => clk, rdclken => '1', rdaddress => addr, q => d_out, rden => '1', wrclock => clk, wrclken => '1', wraddress => addr, data => d_in, wren => we ); end altera; d173 1 a173 7 library exemplar; use exemplar.exemplar_1164.all; library lpm; use lpm.all; entity dpram is d175 5 a179 2 data_width : positive; addr_width : positive d182 1 a182 1 clk : in std_logic; d184 15 a198 9 r_d_out : out std_logic_vector(data_width-1 downto 0); r_rd : in std_logic; r_clk_en : in std_logic; r_addr : in std_logic_vector(addr_width-1 downto 0); w_d_in : in std_logic_vector(data_width-1 downto 0); w_wr : in std_logic; w_clk_en : in std_logic; w_addr : in std_logic_vector(addr_width-1 downto 0) d200 1 a200 1 end dpram; a201 51 architecture altera of dpram is component lpm_ram_dp generic ( lpm_width: positive; lpm_widthad: positive; lpm_numwords: natural := 0; lpm_type: string := "lpm_ram_dp"; lpm_indata: string := "REGISTERED"; lpm_outdata: string := "UNREGISTERED"; lpm_rdaddress_control: string := "REGISTERED"; lpm_wraddress_control: string := "REGISTERED"; lpm_file: string := "UNUSED"; lpm_hint: string := "UNUSED" ); port ( rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0); rdclock, wrclock: in std_logic := '0'; rden, rdclken, wrclken: in std_logic := '1'; wren: in std_logic; data: in std_logic_vector(lpm_width-1 downto 0); q: out std_logic_vector(lpm_width-1 downto 0) ); end component; begin altera_ram: lpm_ram_dp generic map ( lpm_width => data_width, lpm_widthad => addr_width, lpm_numwords => 2 ** addr_width, lpm_type => "lpm_ram_dp", lpm_indata => "REGISTERED", lpm_wraddress_control => "REGISTERED", lpm_outdata => "UNREGISTERED", lpm_rdaddress_control => "UNREGISTERED", lpm_file => "UNUSED", lpm_hint => "UNUSED" ) port map ( -- rdclock => clk, rdclken => r_clk_en, rdaddress => r_addr, q => r_d_out, rden => r_rd, wrclock => clk, wrclken => w_clk_en, wraddress => w_addr, data => w_d_in, wren => w_wr ); end altera; a205 3 library altera_exemplar; use altera_exemplar.all; d207 7 a213 6 port ( d : in STD_LOGIC; clk: in STD_LOGIC; ena: in STD_LOGIC := '1'; clr: in STD_LOGIC := '0'; pre: in STD_LOGIC := '0'; q : out STD_LOGIC a215 25 architecture altera of d_ff is component dffe port ( D : in STD_LOGIC; CLK: in STD_LOGIC; ENA: in STD_LOGIC; CLRN: in STD_LOGIC; PRN: in STD_LOGIC; Q : out STD_LOGIC); end component; signal clrn,prn: std_logic; begin clrn <= not clr; prn <= not pre; ff: dffe port map ( D => d, CLK => clk, ENA => ena, CLRN => clrn, PRN => prn, Q => q ); end altera; -- Sythetizer library. Contains STD_LOGIC arithmetics @ 1.2 log @Major reorganization and some new elements added. @ text @d20 1 d23 1 a23 1 function min(a : integer; b: integer) return integer; d94 1 a94 1 function min(a : integer; b: integer) return integer is d122 7 d292 1 a292 1 rdclock => clk, d377 1 a377 1 rdclock => clk, @ 1.1 log @Initial revision @ text @d19 5 d57 2 d87 63 d223 159 @ 1.1.1.1 log @Inital commit for OpenCores @ text @@