Re: [video] Video Timing generator(RS170) interlaced in VHDL

[maxismsx@hotmail.com]

Dear Sir,

In order to get the detailed interlace timing, use any of datasheets for 
digital video encoders or my article: 
http://www.opencores.com/projects/lite_videocoder/Digital_video_encod
er.PDF

Where, I give a detailed description of PAL/NTSC interlace timing. What 
do you mean by a "half clock cycle??". Normally the interlace timing is 
regulated by splitting the line by preequalisation, serration and 
postequalisation sequence such, that every field with odd number would 
start from the full line and every field with even number would start from 
a half-line. The falling edge of vertical sync is always generated at the 
time of zero subcarrier phase, which corresponds to the beginning of the 
first serration pulse.Serration and equalisation pulses are only valid on 
Composite Sync pulse. Horizontal and Vertical Synchronization must 
have the regular timing. From the HSYNC and VSYNC generation 
standpoint, if you don't need complicated 8/4 field timing, the VSYNC 
must be generated exactly after Thsync/2 of the line number 312 in PAL 
and the line 262 in NTSC and, of couse, exactly at the beginning of the 
line number 0.

Kindest regards,

Maxim





----- Original Message ----- 
From: edwinstuff@y...  
To: video@o...  
Date: Fri, 9 May 2003 06:48:38 -0100 
Subject: [video] Video Timing generator(RS170) interlaced in VHDL 

> 
> 
> I'm currently working on the Video Timing generator(RS170) in VHDL 
> and 
> have problem on the interlaced mode. 
> 
> I know how the non-interlaced mode work but I couldn't get the 
> interlaced mode to work. 
> 
> As I know, even scanning will have half of clock cycle earlier than 
> odd 
> scanning on the front porch. Is that it?  what else I have to 
> consider? 
> The Video board still doesn't recognized it's a interlaced mode all 
> the 
> time. 
> 
> Tried to find information about it but couldn't find it.  Any help 
> is greatly 
> appreciated. thanks 
> 
> edwinstuff@y...  
> 
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